Responsibilities:

1. Verify design and implementation at module/subsystem/chip level

2. Define verification scope and develop verification plan/objective according to specification

3. Test-bench development in using random verification methodologies such as UVM, test case development

4. Collaborate with architects, designer and physical design(layout) for implementation

5. Work for post simulation with gate-level netlist

6. Support pre/post silicon test

Requirements:

1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience

2. Experience in System-Verilog/UVM/OVM/VMM/Specman-E

3. Experience in simulators (Modelsim, NC-sim, VCS)

4. Experience in Perl or others scripting language

5. Knowledge of 2G/3G/4G/5G baseband Architecture, ARM, AHB Architecture is a plus

6. Knowledge of Baseband chip peripheral(PCIE/USB/MIPI/I2C) is a plus

7. Good command of English

上班地址：西安市高新区高新六路38号腾飞研发中心A座4楼