Job description:

l Work on the verification environment using SystemVerilog, UVM or C++;

l Cowork with architects and design engineers on the function/performance test plan.

l Responsible for test cases development

l Implement directed and random testcase in C++/SV/UVM, as well as checkers and assertions

l Debug test cases with designer

l Doing coverage analysis and bug cleanup in regression

Requirement:

l MS with 2+years or BS with 3+ years experience in ASIC/SoC design verification

l Knowledge of complex SoC DV flow from plan to coverage

l Strong C++/SV/verilog development experience

l Strong problem solving and communication skills, team player

l Good knowledge on verification methodologies like UVM is preferred

l Experience in DSP/CPU/Memory controller is a big plus.

l Familiar with scripting languages like Perl, Makefile is a plus

上班地址：祖冲之路张江科技园