To work on Intel next generation CPU SoC using advance process technology.

Need to be familiar with industrial EDA tools from Synopsys andor Cadence Design System.

The candidate is required to implement structural physical designs through synthesis floor planning power grid clock tree design place and route PnR RCextraction timing budgeting and closure to achieve targeted PerformancePowerArea PPA.

Be able to verify the design through comprehensive signoff tools in functional equivalency verification FEV timing performance STA noise layout design rules DRC reliability RV and power.

Qualifications

Bachelor of Engineering degree or a Master of Science in Electronic Electrical or Computer Engineering or equivalent with preferably at least 3 years of experience.

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.