The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO. The job requires partnering and leveraging domain experts across Intel and EDA Eco-System

Your responsibilities may include, but not be limited to:

Establish 3DIC Test Cases across market segments Development of 3DIC construction and validation methodology. Evaluation and feedback of 3D-IC TFM and EDA capabilities

Test Chips validation of 3DIC technology and methodology Design analysis and feedback for 3D silicon and packaging technologies development.
Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.

Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation

Important behavior traits we look for
Self-motivated, out of the box thinker with excellent analytical and problem-solving skills

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• MS degree in Electrical, Computer Engineering OR a PhD degree in Electrical, Computer Engineering.

1+ years of experience in the following:

• VLSI Design

• IP/Chip Physical design optimization, EDA tools and methodologies for optimal Performance/Power/Area/Cost

• Automated place and route (APR)

• Scripting skills using a programming language such as Python, TCL

Preferred Qualifications

• Knowledge of 3D Silicon and 3D packaging technologies

• Power Management Network Design Methodology (PDN IR and EM, Thermal)

• Low-power design and clock gating.

• Reference design and TFM for STCO and 3DIC

• Experience with ARM based IP PPA optimization

• Design for Test (DFT) and Design for Debug (DFD)

• Circuit design and silicon technology. Design challenges in advanced technologies.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.