1. 4/5G modem platform architecture and digital circuit design
2. Whole chip clock, reset, and test plan
3. Low power plan and design
4. Network Layer-2 design
5. Platform integration from RTL to gate level including timing closure and testability
6. Design methodology and integration flow improvement

Requirement

1. Better to have chip integration experience
2. Familiar with front-end or back-end implementaion flow and related EDA tools
3. Familiar with clock plan and clock tree power analysis flow
4. Familiar with low power control concept, techniques and practical implementation
5. Experience of LTE layer-2/3 , Ethernet layer-2/3 or WiFi layer-2/3 design and architecture is a plus
6. Familiar with SoC platform architecture including CPU, Bus, Cache, and DRAM controller