To work on Intel next generation CPU SoC using advance process technology. Need to be familiar with industrial EDA tools from Synopsys and or Cadence Design System. The candidate is required to implement structural physical designs

Your responsibility:

• Understanding & hands on experience in full IC and block level SoC Physical Designs.
• Proactively demonstrating the knowledge in synthesis, FEV, STA.
• Proven the Experience Design floorplan, Clock Tree Synthesis, Power Network Synthesis, Place and Route, Physical Verification (DRC, LVS), DFM, SI(Xtalk).
• Verifying Low-Power design, UPF.
• Performing IR Drop/EM check.

Qualifications

• Minimum 3+ years of experience in the related area. 
• Bachelor or Master’s Degree in Electronics Engineering/Telecommunications, Computer science, Physics electronics.  
• Required technical skills: 
• Synopsys: Fusion/ICC2, StarRC, Primetime, VCLP. 
• Cadence: Innovus, Quantus, Tempus. 
• Mentor: Calibre. 
• Proven experience in IC tape-outs. 
• Deep understanding of the RTL2GDS flow design cycle. 
• Understanding of CMOS process. 
• Excellent scripting skills and CAD automation techniques. 
• Linux/Unix proficient. 
• Additional requirement:  
• Good English skills.
• Strong analytical, problem solving and decision-making skills with the ability to independently draw conclusions. 

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.