Job Description: 

In this position you will be part of a world class Ethernet IP & SOC design team responsible for the design and development of the Ethernet Controllers and Networking Processing of the Network Division Silicon Engineering team. This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge technologies.

Responsibilities for this position include:

• Defining the STA methodology, generating and validating STA constraints
• Defining and implementing timing derates/margins/uncertainties, writing timing constraints for IPs like SerDes/DDR/GIOs
• Define in STA methodologies for FC timing verification for multi-mode , multi voltage SoC
• Responsible for working closely with the clocking team to generate clock balancing guidelines and timing fixes considering all modes all corners and sign-off the design for Tape-out.
• Responsibility might also include running timing and generating ECOs for timing fixes, assisting junior engineers on timing convergence by finding solutions to critical timing paths, as well as including generation of IO timing constraints

Thorough understanding of STA flows/tools like Primetime/Tempus, tools to check and validate timing constraints

Qualifications

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical, Electronics or Computer Engineering or other related field of study with 6+ years of experience in physical design
• 5+ years of experience in physical design/STA methodology in advanced process nodes
• Expertise and in-depth knowledge of industry standard EDA tools Prime time, Fusion Compiler, ICC as well as proficiency in scripting languages, such as, Python, Perl, and Tcl.
• Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, and implement them through ECOs.
• Demonstrate a deep understanding of Static Timing Analysis, timing constraints generation and management, and timing convergence. You are capable of analyzing and converging cross-talk delay, noise glitch, process variation, and electrical/manufacturing rules and the modelling of these effects in deep-sub micron processes required.
   

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.