Silicon Engineering of Intel's Ethernet Product Group is looking for Structural and Physical Design engineers to build Ethernet Network Interface Controller IP and SOCs. The selected candidate will be joining its India team and work on IP/subsystem/full chip level physical design tasks spanning from RTL synthesis to final sign-off. Role in question is for block level physical design engineer who would be responsible for end-to-end physical implementation of one or more blocks starting from RTL synthesis, floorplanning, clock tree synthesis, timing and physical convergence.

Qualifications

Solid track record of taping out multiple chips on advanced process technology nodes such as 7nm, 10nm. Hands-on have experience on industry standard EDA tools such as Synopsys ICC2, Fusion Compiler and/or Cadence Innovus along with PrimeTime, RedHawk and Calibre is mandatory. Thorough technical understanding of backend challenges such as place and route on advanced process nodes, Static Timing Analysis for high frequency designs, impact of EM/IR/ESD on yield and manufacturability, low power design methodology and verification, etc are highly desired skills. Candidate should have handled chip level layout verification tasks for more than 1 project. Should have got a good grip physical sign-off strategies and design for manufacturability concepts. Candidate should possess good communication skills to thrive in a multicultural environment and be able to manage ambiguity and schedule challenges. Must be a team player. Bachelors / Masters in Electrical (EE)/Electronics (EC) Engineering with specialization on Microelectronics/VLSI Design and/or related domains along with minimum relevant industry experience of 10+ years

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.