In this internship you will be a member of the Xeon Engineering Group (XEG) team participating in the design of future generation Intel Xeon SoC's and associated IP's.

Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.

Responsibilities include, although not limited to:

• Work with senior members of the team who develop the custom constraints for driving synthesis and auto-place and route (APR) tools to implement and optimize the design a s a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development)
• Developing chip floor plan, power/clock distribution, chip assembly and Place and Route, timing closure, power and noise analysis and back-end verification across multiple projects.
• Using tool suites such as: ICC2, PrimeTime, Design Compiler, Fusion Compiler
• Interacting with a diverse team engineers
• Working closely with the micro-architecture, RTL and custom circuit teams to converge the design to project targets and work on methodology

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

The candidate must be pursuing a Masters degree in Electrical Engineering, Computer Engineering or Computer Science

3+ months of experience in:

• Synthesis, static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis
• Scripting and programming experience using one of of the following: Perl, Tcl, Python and Make

Preferred Qualifications

• Knowledge of EDA tools like ICC2, PrimeTime, Redhawk-SC, Innovus and Tempus

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

Virtual US

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$52,000.00-$147,000.00

Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.