Plesae use this as the JD: Looking for Physical design/implementaiton engineers with proven skills in Synthesis and/or physical implementation (Floorplanning, place and route, timing closure) areas. The candidate must have worked at IP or at SoC level with familiarity with Intel/TSMC process nodes. Working with analog/mixed-signal IPs in the physical design domain would be a huge plus. The candidate should be willing to learn and a good team player.
Qualifications
B.E. (Electronics ) from a reputed institute is a must. Masters would be preferred. At least 5-10 years of work experience working on physical design
Inside this Business GroupIP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Legal Disclaimer:
Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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