Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world!

The Pre-Si System Integration and Validation Engineer creates emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools. In addition, the engineer:

• Defines and documents RTL changes required for emulation/FPGA.

• Develops hardware and software collaterals and integrates it with the emulation/FPGA model.

• Tests and debugs the emulation/FPGA model and collaterals.

• Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation.

• Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.

• Interfaces with and provides guidance to preSilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency.

• Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.

Good interpersonal skills and the ability to work in a highly cooperative team environment across many time zones are also desirable.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 6+ years of experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience:

• Strong software skills with experience using 1 or more of the following Ianguages- System - Verilog/Verilog, Perl, C/C++, Python.

• Experience with emulators such as ZeBu, Palladium and/or Veloce for large scale designs

• Computer architecture, design principles, validation methodologies and tools

• Debugging and isolation techniques including writing checkers, monitors, assertions, verdi and necessary DPI interfaces for co-emulation environments.

Preferred Qualifications

• CPU, Coherency, reset, Global Flows, Power management, memory, PCIe highly desirable

• Strong debug abilities, good interpersonal skills and the ability to work in a highly cooperative team environment across many time zones are also desirable.

• Prior experience in System Validation is a plus.

The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.

Other Locations

US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.