Intel's Programmable Solutions Group (PSG) Custom IP Solutions Engineering (CISE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Intel's FPGA devices. These solutions are provided as highly-configurable intellectual property (IP) cores that are fully integrated with Intel PSG's software CAD tool, Quartus Prime.
External Memory Interface IP (EMIF) is one category of important IP Cores. Most customer applications require storage or buffering of large amounts of memory. Thus, Memory Interface IP for DDR4, DDR5, or High-Bandwidth Memory (HBM) becomes a critical component of most electronic systems. Another class of IP cores we build are for customized chip-to-chip interfaces. Intel PSG's IP cores provide configurable access to these high-speed, high-bandwidth memory devices and chip-to-chip interfaces. The constantly rising speed and complexity of memory devices and other chip-to-chip interfaces presents a challenging design problem that requires system-level knowledge of silicon, software, IP, and customer applications.
As an IP Design Verification Engineer, you will work with a team of engineers to develop and verify state-of-the-art Memory Interface or chip-to-chip IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.
Your specific responsibilities will include, but are not limited to the following:
Architecture and implementation of scalable validation environments and test content.
Planning and reviewing test plans.
Developing comprehensive verification solutions encompassing traditional UVM-based DV and static verification tools.
Driving verification methodology initiatives within the team, aligning with best known methods across PSG.
The candidate should possess the following behavioral traits:
Strong skills in communication, initiative, innovation, and teamwork.
Highly motivated to learn and adapt to fast-changing technologies and environments.
Excellent problem solving skills and attention to detail.
Demonstrate fundamental values such as accountability, integrity, and a winning mindset.
Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations.
Qualifications
Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Education
Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Minimum Qualifications
5+ years of relevant experience, experience should include:
Verification of RTL design with Verilog and/or VHDL.
Preferred Qualifications
Experience in one or more of the following is considered a plus.
Software programming and/or scripting languages.
FPGA
Memory Interfaces
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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