You will be responsible for the full life cycle of verification, from planning to test execution and including collecting and closing coverage. You will closely interface with architecture and design teams to understand design/product requirements and develop comprehensive test plans and you will conduct/participate in test plan and test reviews, develop verification components and tests, and triage failures.

Responsibilities include, but are not limited to:

• Developing pre-Silicon functional validation tests to verify system will meet design requirements.
• Creating test plans for RTL validation, defining, and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
• Analyzing and using results to modify testing.
• The leader in this position develops scoreboard, monitors, checkers for IP.
• Debugging failing signatures.
• Analyzing coverage holes to reach 100% functional coverage.
• Reviewing test plans for all the IP blocks and tracking progress to milestones.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Candidate must be currently pursuing a Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM fields (documentation related to Bachelor's degree completion will be required). 
• 6+ months of experience in pre-Silicon verification or RTL development.
• 6+ months of experience in system Verilog , UVM, and/or OVM based verification methodologies.
• 1+ years of scripting experience.

Preferred Qualifications:

• Experience in pre-Silicon verification.
• ASIC design/validation experience in front end processes including RTL development, functional and performance verification.
• Experience in verification of design blocks (IP) for system-on-chip (SoC) components.
• Experience in system Verilog , UVM, and/or OVM based verification methodologies.
• Experience in object-oriented programming concepts, coverage based random validation.
• Scripting experience.
• Experience developing scalable and portable test bench.
• Experience with Waveform debugging with latest EDA tools, root-cause bugs independently.
• Advanced English level.

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.