To work on Intel next generation CPU SoC using advance process technology. Need to familiar with industrial EDA tools from Synopsys and/or Cadence Design System. The candidate is required to implement structural physical designs through synthesis, floor planning, power-grid, clock tree design, place and route (PnR), RC-extraction, timing budgeting and closure to achieve targeted Performance/Power/Area (PPA). Be able to verify the design through comprehensive sign-off tools in functional equivalency verification (FEV), timing/performance (STA), noise, layout design rules (DRC), reliability (RV) and power.

Qualifications

Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering or equivalent with preferably at least 1 years of experience.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

Malaysia, Kulim

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.