-Understanding of Scan RTL architecture, scan design and methodology to deliver scan enabled netlist (scan synthesis). -Analyze netlists for scan insertion and scan design to meet coverage goals and providing feedback for coverage improvement. -Perform scan coverage analysis and debug with Spyglass-DFT or other ATPG tools. -Scan RTL and GLS test validation to ensure scan quality design deliverables. -Creates, simulates and verifies automatic generated test patterns (ATPG) using industry standard tools, analyze and drive the improvements to test coverage. -Coordination of Scan/ATPG collaterals with IP provider. -Deliver validated scan patterns to post-Silicon High Volume Manufacturing (HVM) partner teams for silicon testing usage. -Partnership with post-Silicon High Volume Manufacturing (HVM) Team to enable Scan DFT test capability in silicon. -Support debug of any test content failures in the post-Silicon/HVM environment.

Qualifications

-Possess a Bachelor's Degree of Engineering or a Master's Degree of Science in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of experience. -Good communication skills to work with cross-geo teams.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

Malaysia, Kulim

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.