Come join Intel's FPGA Business Unit Programmable Solutions Group as an ASIC Design Engineer. We make outstanding DDR PHYs for a wide range of applications.
As an ASIC Design Engineer, you will be primarily involved in the microarchitecture and RTL coding of critical blocks that make our PHYs so amazing. This is a unique opportunity where you will get exposure to all phases of the design development, from architecture definition to design and verification to silicon bring up and characterization.
Our team only works on cutting edge state of the art technology. Our projects range from high performance memories such as DDR5, DDR4, LPDDR5 to projects that drive die disaggregation with Intel's Industry leading package technology, EMIB. You can participate in early product definition, microarchitecture, define testing, physical integration, and verification strategy while working closely with CAD and Physical Design teams to identify and address timing bottlenecks.
There are plenty of opportunities in our team to further develop your skill sets and or learn something completely new. Working for an FPGA business unit gives you a rare opportunity to get exposed to software modeling of hardware while still working as a pure ASIC design engineer. Our team also allows you to get exposed to mixed signal high speed designs where you get to interact with world class Analog designers. Mixed signal design is a skill set that every high speed PHY designer will need to have going forward. With us, you will champion the development of best-in-class designs tailored to maximize power performance area KPIs such as mW/GPBS, and GB/MM squared.
Qualifications
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Education
Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Minimum Qualifications
4+ years of total experience inclusive of experience in:
Digital Logic Design / RTL design using Verilog or System Verilog
Preferred Qualifications
Experience with designing state machines, counters, FIFOs, etc.
Experience clock domain crossing related issues.
Experience with synthesis and timing constraints.
Exposure to DFT, scan insertion, Design for Debug.
Experience low power design techniques.
Experience with memory system design DDR4,DDR5, LPDDR4, LPDDR5 is a plus.
6+ years in RTL Design.
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Other Locations
US, California, Santa Clara;Virtual US and Canada
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Annual Salary Range for jobs which could be performed in US, Colorado:
$113,500.00-$170,120.00
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
Get email alerts for the latest"ASIC Design Engineer jobs in San jose"