If you are a strong Logic Design engineer then our Intel Validation Engineering (IVE) department has an amazing opportunity for you!

Test Cards team in iVE/CCS is looking for a highly experienced ASIC/FPGA Design Engineer to lead the development of cutting-edge high-speed protocols IPs: USB, Thunderbolt, DisplayPort and CSI. What will you do? Perform logic design throughout the entire design cycle, RTL coding, simulation and synthesis to generate FPGA based systems for the validation of Intel IPs. Participate in the development of architecture and microarchitecture specifications for the logic components

Qualifications

• Minimum Qualifications:
• 6+ years of experience in RTL/Logic design on ASICs or FPGA IP blocks or SOCs using Verilog or SystemVerilog RTL coding
• Must have a BS or MS in Electrical Engineering, Computer Engineering, Computer Science or related

Preferred Qualifications:

• Experience with Packet Based Protocols such as USB or PCIe is an advantage
• Demonstrable experience in logic design and writing RTL in Verilog or SystemVerilog
• Familiarity with a range of internal and 3rd-party logic design tools
• Strong analytical ability, problem solving and communication skills
• Gate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates
• Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues
• Strong communication and team-work stills.
• Ability to work independently and at various levels of abstraction
• Ability to lead a team of designer

Inside this Business Group

The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.