The Design Implementation for Customers using Structured ASIC technology (eASIC) Team within Intel’s Programmable Solutions Group (PSG) is looking for a senior level ASIC Integration Engineer.

As a senior level ASIC Integration Engineer, you will interact with customers to collect information on RTL and IP and implement the customer code through synthesis, PnR, timing closure, and hand off layout database to the tape out team.

As a ASIC Integration Engineer you will…

• Perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.

• Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.

• Perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.

• Develop environment/infrastructure for automation solutions in ASIC implementation flow.

• May also review vendor capability to support development.

Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

5+ years of experience inclusive of:

• RTL to Netlist Synthesis (e.g. Design Compiler) and/or Static Timing Analysis (STA) (e.g. PrimeTime)

• Scripting language experience (e.g. TCL, Python, Perl, Shell etc.)

Preferred Qualifications

8+ years of experience in synthesis, timing, and one or more of the following:

• Experience in Cross Clock Domain analysis (e.g. Spyglass)

• Experience in DDR timing closure methodology

• Experience in RTL coding or SOC integration.

• Experience in Place and Route Tools

• Experience in Python scripting with strong programming and analytical skills

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.