What you’ll be doing:

• The Sr. verification engineer is responsible for end-to-end verification from IP to Tegra/GPU fullchip for video and computer vision engines.
• Besides the traditional ASIC verification, you will also get the opportunity of embracing High-level synthesis (HLS) verification methodology.

What we need to see:

• BS / MS in electrical / computer engineering and related: 3+ years MS or 5+ years BS.
• Familiar with verification methodology, tools and flow.
• Programming skills in System Verilog, Perl and C/C++.

Ways to stand out from the crowd:

• Fully experienced verification flow:
  • Clearly know the typical milestones and the related verification action and release
  • Ability of using proper metrics to present and monitor verification status
• Complex TB setup experience and skills below
  • SVA, functional coverage group, random constraint, etc.
  • Experience of UVM and System C is big plus.
• Experience on video codec and image processing projects.
• Excellent script skill of Perl, Python or shell.
• Knowledge of Makefile and tree infrastructure.
• Experience of formal verification.
• Fluent English (both written and spoken) and excellent communication skills
• Demonstrated ability to work independently as well as in a multi-disciplinary group environment

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