Our client is a leading semiconductor company.

Oversees definition, design, verification, and documentation for ASIC development.

Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation.

Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.

Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.

Power targets, IP selection, floorplan review etc.

Develop RTL code for chip level in Verilog HDL and make sure functional correct and reusable for different configuration.

Synthesis Participate in SOC IC project logic design

Working with architect to define chip level specification, including clock and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.

Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.

Great career development.

Competitive salary package.