Analog Design Verification Engineer Intern
Texas InstrumentsShanghaiUpdate time: January 1,1
Job Description
实习生
Analog Design Verification Engineer Intern
- (190000O4)Responsibilities:
- Implement the mixed-signal test-benches to apply stimulus and checks to verify DUT behavior.
- Utilize Verilog, Verilog-A, Verilog-AMS to stimulate and check mix-signal circuits.
- Work with the design and systems teams to close bugs as they arise.
Requirements:
- 2020 bachelor in Electrical Engineering.
- Experience in Mixed-signal IC Design.
- Good Communication skills (Written and Verbal).
- Understand the basic Digital and Analog design flow.
- Experience using Cadence, Hspice, Verilog, Verilog A or other simulation tools.
- Coding skill with Perl, OCEAN, etc is a plus.
- Fluent English and native Mandarin are required.
- Summer internship period at least 8 weeks.
Primary Location CN-CN-Shanghai
Work Locations Shanghai > China, Shanghai R&D 2F&3F, 72 Liang Xiu Road Pudong New District Shanghai 201203
Job Engineering - Product Dev
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Temporary
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Job Posting Mar 3, 2019, 4:01:17 AM
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