At Intel, we work every single day to design and manufacture silicon products as the fundamental building blocks that empower people's digital lives. Do you love Contributing to cutting edge IP technology that are efficiently powering up your laptop? Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross-functional teams to deliver IP solutions for products that impact customers' lives?

Intel's Power Sensor and Interconnect IP team under Foundation IP Group(FIG) is looking for an experienced analog designer to contribute in the high performance die to die interconnect IP space for Intel's flagship client/server/chipset/Graphics SOC designs.

Your responsibilities will include but not be limited to:
 

Post silicon IP to SOC customer support:

• Plan and execute post -silicon IP support to SOC with IVE/MPE partners.

• Post silicon debug support of test chip and SOC with IP team support.

• Tracking post silicon sighting and drive the prompt debug.

• Drive QT with post silicon stake holders to ensure IP sightings are addressed in timely fashion.

Pre-silicon IP Design:

• Design responsibilities may consist but not limited to high performance, low-jitter IO interfaces, PLLs, on-die voltage regulators and references, custom power supply networks and other elements necessary to design, verify and productize high performance analog and mixed signal IO/Clocking/Power Delivery solution.

• Architecture, technology path-finding, specification, circuit design, validation, layout supervision, documentation, DFT and DFM, and post silicon validation of analog and mixed signal clock generation units.

• Leading and mentoring of team members and active collaboration with colleagues and partners from adjacent disciplines across the company.

• Partner with cross discipline IP design and execution leads and provide high quality IP delivery/releases to all critical SOC customers on schedule.

• Active collaboration across different IP design disciplines and SOC customers.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Must have a MS or PhD in Electrical Engineering, Computer Engineering or Electrical/Computer Engineering.

• Minimum 10 years general IC analog and/or mixed-signal pre-silicon and post silicon experience.

Preferred Qualifications:

• More than 8 years of general IC analog and/or mixed-signal design experience, preferably in high performance, low-jitter IO and PLL space including at least 4 years of experience leading and/or managing design team and mentoring junior engineers.

• Proven track record in the complete life cycle of a high speed IO product from definition, design, tapeout, debug, testing, yield analysis, to product qualification.

• Expertise in high speed wire-line transceiver PHY design, including Tx/Rx driver, equalization, PLL, DLL, clock distribution, CDR, jitter budgeting analysis, etc.

• Familiar with at least one of the major high speed I/O protocols, such as PCI-E, SATA, SAS, DDR4/5, 10GbE/100GbE, etc.

• Experiences with mixed signal design and modeling techniques.

• Experiences with high speed IO debug, testing, and standard compliance.

• High-speed test equipment (i.e., network analyzers, spectrum analyzers, digital sampling oscilloscopes, signal generators, BERTs).

• Good understanding of nano-scale silicon process technology, devices, packaging and the interactions with high speed IO design.

• Working knowledge of analog layout techniques, including matching, parasitic optimization and floor planning.

• Familiar with industry standard design software for schematic capture, simulation, layout and physical verification, such as Cadence SpectreRF /Ultrasim /AMS Designer /Virtuoso.

• Proven track record of technical leadership and project execution management.

• Working experiences of interfacing with process/design automation/debug/testing teams and customers.

• Good l communication skills are extremely important.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara;US, Massachusetts, Hudson

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.