Intel's recently announced IDM 2.0 strategy includes a plan to significantly expand the manufacturing network, establishing new capacity and capability to meet the accelerating global demand for semiconductors. The external Packaging and Assembly Engineering team (EPAE) is responsible to introduce and qualify external assembly technologies for products based on newest Intel silicon nodes and thus plays a critical role in this strategy.

Qualifications

A degree in Electrical Engineering or Physics from University / University of applied sciences Work experience of at least 5 years and profound expertise in chip package interaction (CPI) The candidate needs to be familiar with CPI related failure modes and the impact of design, materials and critical process steps. Profound skills in assembly technologies including die prep and bumping. Experience in project management in international teams Proficient written and verbal communication skills in English

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.