CPU PPA and PNR Engineer
QualcommXinzhuUpdate time: August 26,2019
Job Description
Location
Taiwan - Hsinchu

Job Overview
We are looking for bright asic engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-7nm process for mobile space. Responsibilities: - Participate on a project involved in the development of High performance CPU, with emphasis in Power, Performance, Area optimization in Place and Route. - Develop CPU floorplan, run and optimize the Place and Route flow, evaluate timing and power at placement, clocktree and routing. - Create design of experiments and do detailed comparison analysis to improve quality of results. - Work closely with Frontend, PPA, CAD, low power and automation teams to optimize performance and power - Tabulate metrics results for analysis comparison - Generate Power and Performance curves

Minimum Qualifications
Extensive experience in Physical Synthesis (RC/Genus), PnR (Innovus) is an absolute must.
  • Complete asic flow with low power, performance and area optimization techniques

  • High speed CPU implementation

  • Experience with STA using Primetime and PTPX required

  • Perl/Tcl scripting is required

  • Strong problem solving and asic development/debugging skills

  • Preferred Qualifications
    Experience with CPU micro-architecture and their critical path - Low power implementation techniques experience - Experience of multiple power domain implementation with complex UPF/CPF definition preferred


    Education Requirements
    Required: Bachelor's, Electrical Engineering or equivalent experience
    Preferred: Master's, Electrical Engineering or equivalent experience

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