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Western Digital is an equal opportunity employer. Western Digital does not discriminate on the basis of race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Equal Employment Opportunity is the Law" poster.

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1. Working on synthesis/STA constraint build, WL/DCT/DCG synthesis, formal equivalence check/debug, STA analysis, floor plan quality check, RTL/netlist power analysis , implementation flow build/improvement, EDA tool evaluation and support RMA case root causing and PPA evaluations.

2. Has Physical Design experience is best (Perform complete netlist to GDS physical design steps which include floor plan, APR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. Candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements.)

3. Co-work with cross sites/function teams on constraint, timing closure and physical design.

4. Provide suggestions to cross function teams from implementation point of view.

5. Working with ASIC design and architecture teams to understand functionality of logic blocks of SSD controller

6. Comprehending ＂big picture＂ at the ASIC architectural and system level as well as executing at the detail block level.

1. Master/Bachelor's degree in Electrical Engineering or Computer Science.
2. Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred.
3. Knowledge of ARM AMBA Bus protocols
4. Knowledge of C and SystemVerilog.
5. Knowledge of ASIC implementation flow from RTL to netlist/GDS
6. Experience in ASIC silicon issue debugging
7. Familiar with scripting language like Perl/Python/Tcl

Because Western Digital thrives on the power of diversity and is committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution, we are committed to giving every qualified applicant and employee an equal opportunity.  Western Digital does not discriminate against any applicant or employee based on their protected class status and complies with all federal and state laws against discrimination, harassment, and retaliation, as well as the laws and regulations set forth in the "Equal Employment Opportunity is the Law" poster.