In this role responsibilities include, although not limited to:

• Lead Pre-Si validation in various functional areas of SOC or IP, including Pre-Si validation plan development, and execution on validation platforms, which would include simulation, FPGA, and Mixed Signal.

• Drive adherence to Intel Program Life Cycle requirements for validation to program milestones, including preparation fo post-Si activities.

• Development of test bench infrastructure and validation content.

• Coordination with SOC partners to align on expectations and dependencies for deliverables, which also includes development of tracking metrics and reporting outwards to stakeholders.

• Collaborate with design and architecture teams to align on features, scope of features and changes, staging of feature development, and validation coverage expectations.

• Representation of the execution and status of pre-Si validation execution to architecture, management, and other stakeholders.

Qualifications

Minimum qualifications to be considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates for this position.

Minimum Qualifications:
At least a Bachelor's degree in Computer or Electrical Engineering and 6+ years of industry experience.

OR

Master's Degree in Computer or Electrical Engineering and 4+ years of industry experience.

• RTL design validation experience including developing unit or system level test benches and test-plan generation.

• Experience in test-bench component development such as monitors, scoreboards/checkers, and BFMs (Bus Functional models).

• Proficiency in HDL such as Verilog/OVM and/or UVM/System Verilog.

• High level of problem solving and debugging skills.

Preferred Qualifications:

• Experience in validation at SOC level with global flows such as Reset, DFD/DFT, Clocking, or Power Management.

• Experience in validation with power-aware models and/or X-propagation.

• Experience in mixed-signal validation techniques and tools.

• Experience with embedded firmware based validation.

• Familiarity with hardware design flows and tools: CDC, Lint, Synthesis, logic equivalence, timing, and power estimation.

• Experience with development of FPGA or Emulation-based platforms.

• Experience with post-silicon debug techniques.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, California, Santa Clara;US, Massachusetts, Hudson;US, Oregon, Hillsboro;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$132,940.00-$199,800.00

Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.