In this role you will be a key member of a team participating in the design of a future generation Intel microprocessor. Responsibilities for this position will include any of the following activities:
Generating fullchip-level and sub fullchip-level timing reports using industry-standard STA tools and aiding in timing convergence
Aid in timing convergence by running critical path analysis and identification of logic structures requiring custom design and layout for timing optimization
Clock tree synthesis in Synopsys or Cadence APR tools
Design and implementation of custom global clock distribution
On-die power delivery convergence, including EM/IR analysis
Block floor planning and RTL to gate level netlist generation through synthesis
Validation of physical design including DRC/LVS, RV and Formal equivalence verification
Scripting to automate tasks and improve debug efficiency
The ideal candidate will also exhibit behavioral traits that include:
Working well in a team and being productive under aggressive schedules
Good written and verbal communication skills
Self-motivation and good organizational skills
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
This position is not eligible for Intel immigration sponsorship.
Candidate must have a Bachelor's degree in Computer or Electrical Engineering and experience in the following:
VLSI
Physical Design
Static Timing Analysis
Computer Architecture
Knowledge of scripting languages (tcl, perl, python)
Preferred Qualifications:
1+ years experience in any of the following areas:
Timing verification using industry-standard EDA tools for timing analysis
Noise, cross-talk, OCV analysis
Clock tree synthesis and custom clock design
Floorplanning
Formal equivalence, DRC/LVS, IR and electro-migration checks
Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Other Locations
US, Oregon, Hillsboro;
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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