Understands IP life cycle flow, QA checks, its methodology & collaterals . Ability to review requirements to suggest/propose internal Vs External IP against technical , commercial trade offs. Closely interacts with internal & external IP vendors & integrates with SoC team -Arch, Design, Validation, Emulation, DfX, SD , Post Silicon & SW . Good understanding of IP qualification, Release methodology & IP integration requirements is must. SoC design flow -Logic design, Val, emulation, DfX, SD(LV, PV, RV) knowledge is important . Should be able to track IP deliveries against PDK, Change requirements is required.
Qualifications
Bachelors or Masters degree in Electrical, Electronics or Computer Engineering, or other related field with 5+ years of relevant industry experience, including at least 5 years of RTL design experience 1. In-depth knowledge of digital logic design, chip architecture and microarchitecture 2. Strong in communication, leadership, investigation, problem solving & analytical/debugging skills 3. Proficiency with RTL coding and checkers (LEC, CDC, DFT) 4.Well versed in interface timing budget & clock domain crossing design 5 .Knowledge of VCS, Co-sim, Conformal LEC is an advantage 6. Familiarity with processor designs, major IPs & sub-systems
Inside this Business GroupThe focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center. Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.
Other Locations
India, Bangalore
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