About DE organization:

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies.

About the role:

As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools.

Responsibilities:

• Define technical specification for Intel advance technology features to enable Intel-specific and industry standard EDA design tools. Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders.
• Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
• Joint effort with partners in DE organization to evaluate and isolate performance contributors for technology features as part of enablement.
• Build and qualify Process Pathfinding Kits and tools with quick turnaround time.
• Drive innovation and initiatives to enhance existing automation, tools and methodology.
• Identify and analyze problems, plans, tasks and solutions.
• Cultivate and reinforce appropriate group values, norms and behaviors.
• Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity.

Qualifications

Minimum Qualification:
BS in EE/CE with 5+ relevant industry experience OR MS in EE/CE with 3+ relevant industry experience OR Ph.D. in EE/CE with 1+ relevant industry experience in the following areas:

• Parasitic Extraction, Device Modeling and Simulation tools/flows
• Custom design flow and related EDA tools
• CMOS device physics, process technology and design rules
• Tools, flows, and methodology for optimal Product Performance/Power/Area/Cost (PPA)
• one of the following: Python, PERL, TCL

Preferred:

• Familiar with Reliability verification, ESD concepts, Standard Cell Library and Memory Architectures

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will require an on-site presence.