Responsibility:

Work together with algorithm team and design team to develop testplan and testcases for various blocks in our Read Channel products.

Maintain and help improve UVM based verification environment.

Develop checker/driver and test cases to verify read channel designs.

Research on some advanced verification technology such as assertion based formal verification.

Requirement:

Major in EE, CS or related.

Familiar with Verilog and RTL design

Familiar with System-Verilog and UVM verification methodology

Familiar with script languages(perl,tcl,sh etc.) is a plus

Familiar with digital signal processing knowledge is a plus

Good problem solving and communication skills

Good written and spoken English. Be able to work together with global team.

上班地址：张江高科技园区科苑路399号