工作年限:
五年以上

所属部门:
阿里集团

学 历:
本科

招聘人数:
若干

岗位描述:

• Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
• Contribute significantly to verification infrastructure development
• Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements

岗位要求:
Masters degree desired, Bachelor's degree in CS/EE is required. 5+ years of relevant experience in ASIC verification field.

• Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
• Fluent in System Verilog and scripting languages such as Python or Perl.
• Must have intimate knowledge of UVM methodology.
• Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
• Knowledgeable about assertions and functional coverage
• Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
• Very good communication skills and ability and desire to work in a geographically diverse team environment.
• Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs