Responsibility:

? Develop micro-architecture for GPU blocks based on architectural requirement.

? Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration.

? Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.

? Analyze gating efficiency report to improve RTL quality

Requirement:

? MS degree of EE with 5+ years working experience in ASIC Company.

? Expert of Verilog RTL design and has experience of large digital ASIC project.

? Familiar with front-end EDA tools and flows.

? Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)

? Fluent English on talking, presentation and writing documents.

? Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.

? Can solves complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation

? Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus)

? Possesses specialized knowledge of Computer graphic knowledge (a plus)

上班地址：张东路1387号46-49栋