? Design and verification of digital IP for SOC

? participate in logic synthesis, timing analysis, LINT and CDC check.

? support validation team with chip debugging.

? Bachelor or master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines

? Good knowledge and experience in digital IC design, proficient in Verilog language.

? Good Communication skills (Written and Verbal). Fluent English and native Mandarin are required.