About the team:

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the DE Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools.

About the role:

As Electrostatic Discharge (ESD) Design Automation Engineer, you will be working with the following:

• ESD tools and flows methodologies, ESD technology and design such as the function of ESD protection circuits, design of various types of I/O circuits, and full chip integration and assembly
• Analog design methods and reliability verification flows such as EM/IR, Aging, EOS, and physical verification flows such as LVS, DRC, Density
• Generate specs working closely with other stakeholders and code to the spec
• Applies advanced troubleshooting to automation system problems
• Drives continuous improvement efforts to meet automation systems health goals, as well as emerging capability needs

Qualifications

Minimum requirements:

Master's degree in Electrical Engineering, Computer Engineering or related engineering field with 2+ year of experience in the following areas:

• Semiconductor device physics and design rules
• Industry-standard extraction and simulation tools.
• At least one of the following: Python, PERL, TCL

Preferred:

• ESD concepts for technology/design methodologies and related EDA tool
• Physical verification flows: LVS and DRC.
• Tools, flows, and methodology, for optimal Product PPAC (Performance/Power/Area/Cost)

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.