Ideal Candidate

Candidate is preferred to be MS EE with minimum of 1+ year, or BS EE with minimum of 3+ years experience in digital ASIC/SOC design verification. Can help manager to execute plans in projectwith high quality results.Strong communication capability in English is required.

Your daily work such as...

• Work with global architecture and designers to get a full deep insight on the design under verification.
• Unit/Block/Cluster/Chip level state of the art verification, test bench setup/maintain and methodologydeployment.
• Test case creation to ensure coding coverage meet target.
• Provide clear status ofchip verification progress and issues to management.
• Support DFX verification

We hope you are...

• Has learnt knowledge of Verilog/C/C++/System C/System Verilog
• Verification of large scale ASICs
• Can understand on Object Oriented verification such as UVM/OVM.
• Knowledge of low-power design technique and implementation flow is plus
• Strong cooperation skill with global team with good oral in English on daily basis
• Strong self-motivation
• Be open minded, passion and strong drive
• Excellent team work is required.