Are you eager to shape how reliability is designed into Intel products in highly advanced Si-technologies? Do you want to drive exceptional PPA while securing customer experience over product lifetime? Then you are a good candidate for the position of a Circuit Reliability Characterization Engineer in the Munich based Technology Enabling team. Within an international team of experts you will work on tasks like

• Development and implementation of circuit level stress methodology for model to hardware comparison of aging effects and model enhancements in highly advanced tech nodes.

• Test structure development for device and circuit stress including design and simulation (e.g. Spectre, aging, EMIR, thermal simulation). Further, layout and testchip implementation in collaboration with ODC.

• Setup + verification of lab test bench including adjustments of hardware and stress software (Python-based).

• Definition of test plan, execution of stress tests on testchips and data evaluation (Matlab, Python).

• Comprehensive documentation of stress methodology and reporting of characterization results to project and key stakeholders.

You will become part of a company which continues to change the world through its brilliant people. To reward the amazing contributions of our people we offer a market competitive compensation & benefits package including plenty of family and flexible work benefits (i.e. the opportunity for part time home office work), programs that focus on your health and wellbeing, many development opportunities and enough time to relax, re-charge and retreat.

We believe in flexible working models. Intel is an equal opportunity employer.

Qualifications

• University / University of applied sciences: Bachelor/Master degree in Physics, Electrical Engineering or similar required

• Profound experience with design, verification (pre-Si) and characterization (post-Si) of fundamental circuits e.g. ring oscillators

• Alternatively, profound experience with device and circuit reliability stress methods (wafer level, package level)

• Experience with analog design verification and simulations (e.g. in Cadence Virtuoso, Spectre)

• Applied programming to solve engineering tasks in state of the art languages / software (e.g. Python, Matlab or similar), experience with lab automation beneficial.

• Good knowledge of semiconductor physics, devices and silicon process technology preferably in highly advanced FINFET technology nodes

• Enthusiastic about continuous learning

• Passionate communicator with strong presentation skills

• Language: English fluent (verbal and writing), German beneficial

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.