【Responsibilities】

1.Implement radar signal detection and processing functions on FPGA platform for system demonstration as well as pre-silicon emulation/verification.

2.FPGA RTL design with Verilog HDL, mapping/PAR/timing closure with Synplify_pro/ISE/Quartus

3.FPGA development flow creation and documentation based on ASIC design

4.Onboard debugging with HW/SW team

5.Specify requirements for the next generation FPGA/HW platform (including device capacity and interfaces and associated debug/add-on hardware/daughter-cards)

【Requriements】

1.Bachelor required, and Master preferred

2.At least three years of experience in logic design for FPGA/ASIC

3.FPGA tool chain (RTL, P&R, timing analysis/closure, power analysis, etc)

4.Expert level proficiency with RTL design modification, logic simulation and implementation tools for large complex designs

5.Good understanding of FPGA timing and FPGA (Cyclone/Zynq) architecture/clock system

6.Good knowledge and working experience with commonly used IC devices

7.Familiarity with common lab equipment and tools

8.Good verbal and written communication skills and communicates well across functional groups

9.Experience in wireless communication SoC is a plus

10.Experience in radar system is a plus

上班地址：盛夏路666号上投盛银大厦E幢904室