Intel Programmable Solutions Group (PSG, formerly Altera) is seeking committed, customer focused and motivated candidates to join its Customer Experience Group as an Application Engineer specializing in FPGA Design and Debug, FPGA Design Flows and FPGA Timing Analysis.

Every day we are committed to creating a delightful customer experience with Intel® FPGA Software Tools. We collaborate with a wide range of teams to create this experience by ensuring high quality technical support, by converting customer feedback into product requirements and by developing technical collateral for our products.

Responsibilities include, but are not limited to:

• Deliver technical support to resolve FPGA design and application issues. This may include Intel® FPGA Software tool issues related to design flows, compilation, simulation, silicon performance, internal/external intellectual properties.

• Develop strategies to solve high complexity problems.

• Develop technical collateral, reference designs, demos, trainings, videos to demonstrate the usage of Intel® FPGA products.

• Create product and customer requirements for Intel FPGA Software Tools.

• Evaluate Intel® FPGA Software tools and provide input to development teams.

The ideal candidate should exhibit the following behavioral traits:

• Problem-solving.

• Patient in helping others.

• Time management.

• Quality.

• Attention to detail

• Highly motivated to learn. 

• Adapt to fast-changing technologies and environments.

• Communications skills.

• Drive issues to closure.

• Do not mind digging for answers until you have found a satisfactory one.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM field with 5+ years of applications engineering or system design experience, or

• Master's degree in Electrical Engineering, Computer Engineering, or related STEM field with 3+ year(s) of applications engineering or system design experience, or

• PhD degree in Electrical Engineering, Computer Engineering, or related STEM field.

With the following experience:

• 3+ years of experience with FPGA/ASIC design using HDL.

• 1 + years of experience with Scripting programming language

• 3+ years of experience with Standard EDA Tool Flows, System Design, Design Synthesis, Timing Closure, Design Optimization

Preferred Qualifications

• Experience with building large system level designs involving complex FPGA IPs.

• Experience with Intel® FPGA Platform Designer Tool or any other equivalent tool.

• Experience in Simulation and Verification Tool Flows.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here