The Custom Structured ASIC Engineering Group within Intel Programmable Solutions Group is seeking a versatile and talented candidate to be part of Intel's next generation Custom Structured ASIC Development Team.

In this position, you will play a critical role in developing DDR3/4/5 PHY IP solutions for Structured ASIC platforms. You will collaborate across Design Engineering, Validation and Architecture to define and implement best solutions for our customers.

In this role your responsibilities will include but not limited to:

• Implement firmware algorithms for DDR3/4/5 PHY IP and test them pre and post silicon

• Maintain and offer support for existing firmware

• Develop specification and test plans based on hardware/firmware co-design

• Develop and validate APIs to ensure a smooth interaction between various components and debug tools

• Work closely with Hardware, Implementation and Test Team to integrate all desired features

You will become part of a company which continues to change the world through its brilliant people. To reward the amazing contributions of our people we offer a market competitive compensation & benefits package including plenty of family and flexible work benefits (i.e. the opportunity for part time home office work), programs that focus on your health and wellbeing, many development opportunities and enough time to relax, re-charge and retreat.

 

We believe in flexible working models. Intel is an equal opportunity employer.

Qualifications

Minimum Qualifications:

• Bachelors or Master's degree in Computer Science, Computer Engineering or Computational Science

• Strong C/C++ and python programming skills

• Experience with HW/SW co-design

• Good problem-solving skills and debug capabilities

• Good English communication skills and teamwork

• Familiarity with revision control systems such as GIT / Perforce

• Highly motivated, able to work in collaborative environment with cross-organizational teams as well as independently

Preferred Qualifications:

• Experience with DDR3/4 interfaces, DDR3/4 PHY architecture or memory controller

• Experience in pre and post silicon validation with focus on DDR interfaces

• Experience with Verilog/SystemVerilog is a big plus

• Experience with waveform analysis and debug using VCS, NCSim or Questa simulators (pre-silicon), as well as oscilloscopes and signal analyzers (post-silicon)

• Experience with debug interfaces (mainly JTAG) is considered a big plus

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.