• As a Foundry Technology Pathfinding Physical Design Engineer, you will lead pathfinding chip-level PPA analysis of monolithic and disaggregated technologies.
• You will interface with a diverse group of experts spanning architecture, design, and foundry providers to identify the set of technologies that meets product needs.
• As a Physical Design Engineer you may interface with the standard cell, memory, architecture and product teams to co-optimize PPA.
• Lead block-level and full-chip PPA assessments for future technology nodes.
• Responsible for modifying and generating PDK collateral. Responsible for taking the block from RTL to GDS including synthesis, place and route, clock tree synthesis, timing optimization, timing closure and signoff, IR drop analysis, physical design verification.
• Responsibilities may include:
  - Develop new insights to improve PPAC in emerging monolithic technologies and heterogeneous system integration technologies through physical design.
  - Develop physical design methodologies and flows for disruptive technologies, modify or create design collateral to carry out design-technology co-optimization (DTCO) / system-technology co-optimization (STCO) to take the designs from RTL to GDS. Perform synthesis, CTS, PnR, STA, timing closure, sign-off, IR drop analysis.
  - Generate and maintain PDK collateral. Evaluate emerging ideas by using fundamental analysis and make sound recommendations to the larger team.
  - A successful candidate will demonstrate: Deep knowledge of PPA assessment methodologies, design-technology co-optimization, system-technology co-optimization.
  - Deep understanding of physical design verification (DRC, LVS) at block and full-chip level.
  - Proficiency in programming and scripting languages like Python, Perl / TCL, or similar languages.
  - Familiar with emerging technology trends and competitive landscape for both monolithic and heterogeneous integration technologies.
  - Good problem-solving and communication skills

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This Position is not eligible for Intel immigration sponsorship.

Minimum Qualifications:

• 5+ years of hands-on experience in physical design (synthesis, clock-tree synthesis, place and route, static timing analysis, power, and IR-drop analysis) and PDK development in advanced CMOS technologies
• BS in Electrical Engineering, Computer Science, or related fields

Preferred qualifications:

• MS or PhD in Electrical Engineering, Computer Science, or related fields
• Experience in machine learning / reinforced learning / artificial intelligence aided physical design is a plus

Inside this Business Group

Intel's Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.