Intel NM will be ramping the Foveros Interposer process at the site in 2022 and beyond. The site is responsible for successfully executing this technology transfer and ramp into high volume production.
In this role you will contribute to segment team leadership, coordinating and driving integrated parametric, defect and cycle time matching. Additionally, you will help solve key technology issues that arise through daily troubleshooting, system level improvements, and excursion containment and follow-up.
Job Description:
The Foveros technology team is looking for a backend process integrator (PI) to help enable successful ramp of the FOVEROS process from low to high volume and subsequently support the process on an ongoing basis.
In this role you will:
Help lead/support an integrated Segment Team comprised of cross-functional engineers
Lead resolution of technology matching issues within segment
Define troubleshooting plans for issues that arise and own execution of material through the line
Collaborate with module engineers to address in-line issues
Work with Yield Analysis and Device engineering to ad-hoc troubleshoot issues
Own segment health through ramp and into high volume manufacturing
Planning and conducting experiments and data analysis to optimize and characterize process and understand sources of variation within the fab to improve process stability/capability.
Developing solutions to problems utilizing formal education, statistical knowledge, experiment design, industry literature, and problem-solving tools.
Developing strategies to resolve difficult problems and establishing systems to deal with these problems in the future.
The ideal candidate should exhibit the following behavioral traits:
Demonstrated capability working in a high performing team culture which includes: excellent teamwork and leadership skills, demonstrated problem solving and prioritization skills
Fundamental understanding of electrical test structures, Sort bins, Class test, device characteristics, product architecture, process interactions and packaging technology
Understands concepts of process capability, true spec, and variance
Qualifications
Minimum Qualifications
BS, MS, or PhD in Chemical Engineering, Electrical Engineering, Material Science, Microelectronics Engineering, Mechanical Engineering, Chemistry, or Physics or Related field.
3+ years previous experience in the semiconductor industry
Preferred Qualifications:
1+ years of experience with backend processing and tools
1+ years of experience with design of experiments (DOE) principles
1+ years of experience in data analysis and statistical process control (JMP, SQL, PCS)
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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