If you have 5+ years of experience in SD \ HW Backend and want to influence the world of SD \ HW Backend by exploring, developing and defining new ways to do SD \ HW Backend work, working side by side with experts in this field.

Who we are:

Central BE TFM Design team which is part of the Client Development Group working on the next generation CPU products for mobile and desktop market is looking for a senior Hardware Back-End Engineer who is excited about solving high frequencies and low power design challenges.

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What will you do:

Define the methodologies and flows and verifies that the full RTL2GDS flow which involves Synthesis, Equivalence, APR , Quality meets the product needs and quality.

Lead different technical reviews activities and definitions involving backend, timing, power, flow planning, DFX, libraries.

Qualifications

• 5+ years of experience in System on Chip Hardware BackEnd design
• Understanding of construction flow: Synthesis, Place and Route, LO verification
• Understanding of signoff activities (STA, Power integrity verification, Reliability verification, IR drop and Cross Talk analysis )
• Understanding of formal verification tools , mainly for logic equivalent verification (LEC)
• Understanding of clocks distribution and implementation techniques in block level
• BSc in Electrical engineering from known University

Advantage:

• Experience in design for power techniques
• Experience in high frequency design convergence
• Experience in full chip activities (routing, clocks, STA)

Inside this Business Group

The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

Other Locations

Israel, Haifa

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.