Creates emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation easeofuse and improvement of equipment utilization.

Qualifications

Required B.Sc / M.Sc degree in Electrical Engineering, Computer Engineering or Computer Science Good multi-tasking skills Team-player, great communication skills Scripting or programming experience: Python, Linux tools Advantage experience in RTL coding/debug related position: Verification/Validation/Design Familiarity with Synopsys tools Programming skills, virtual platforms Familiarity of Intel CPU architecture, specifically in the area of uncore. Experience in emulation Zebu or Haps, SLE environment

Inside this Business Group

The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.