岗位职责:

Responsibilities:

1. Module/block specification together with architect and other designers.

2. Module/block RTL Coding and system integration with verilog/VHDL.

3. Collaborate with verification engineers for module/block and system integration verification.

4. Collaborate with Physical design(Layout) engineers to ensure design meeting timing and area requirement.

5. Collaborate with DFT engineers for DFT feature.

6. Collaborate with FPGA engineers for prototype the design.

任职资格:

Requirements:

1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of design working experience.

2. Experience in RTL coding(Verilog/VHDL) and logic synthesis.

3. Experience in simulators (Modelsim, NC-sim, VCS).

4. Experience in Perl, or others scripting language.

5. Knowledge of 2G/3G/4G/5G baseband Architecture, ARM, AHB Architecture is a plus.

6. Knowledge of Baseband chip peripheral(PCIE/USB/MIPI/I2C) is a plus.

7. Good command of English.

上班地址：陕西省西安市高新区高新六路38号A座4层