REPLACEMENT REQ-PREVIOUS REQ#JR0209289 Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. The experience listed below may be obtained through schoolwork, classes and project work, internships, military training, and/or work experience. Minimum Qualifications: Candidate must have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 6+ years of experience OR a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science with 4+ years of experience with: Solid understanding of digital design and RTL implementation. Experience in working with architecture and design team to write micro-architecture specs. Experience of ASIC test methodology such as scan insertion, memory BIST and test pattern generation. Experience with industry standard design integration tools and methodologies including Lint, CDC and static power checking. Experience in fixing STA and Synthesis related issues. Willingness to work independently and at various levels of abstraction, and solid analytical skills. Preferred Qualifications: Flow automation scripts using Perl/Python and TCL scripts. Experience of SRAM design. Experience in ATPG patterns verification with gate level simulation, test coverage and test cost reduction analysis. Hands on knowledge in state-of-the-art EDA tools for DFT. Experience in ECO process. Experience of closing backend issues with layout team.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.