The IP (Intellectual Property) Logic Design Engineer performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. They also participate in the development of Architecture and Microarchitecture specifications for the Logic components, and provides IP integration support to SoC customers and represents RTL team.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
- 1+ year of experience in HDL (Hardware Description Language) like System Verilog and other related languages.
- 6+ months of experience in Logic design.
Preferred Qualifications:
- Experience debugging RTL.
- Understanding of power strategies, Clock/Reset domain crossing, and synthesis process.
- Knowledge on Pre-Si verification.
- Knowledge in FPGAs.
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Get email alerts for the latest"IP Logic Design Professional jobs in Guadalajara"