As an Intern member of Intel's Programmable Solutions group, the candidate will be responsible for ramping up to develop an IP prototyping platform with a focus on FPGA interface design for Intel's high speed SERDES products.
In this role as Sub-system IP Prototyping Intern, you must have course background Field Programmable Gate Array and/or RTL (Register Transfer Level) development and/or logic synthesis.
Structured ASIC team:
This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space. Intel® eASIC™ devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.
Learn more about us:
https://www.anandtech.com/show/16266/intels-new-easic-n5x-series-hardened-security-for-5g-and-ai-through-structured-asics
https://www.intel.com/content/www/us/en/products/programmable/fpga-vs-structured-asic.html
https://www.intel.com/content/www/us/en/design/products-and-solutions/structured-asics/overview.html
Responsibilities will include, but are not limited to:
Support developing a custom IO on Field Programmable Gate Array using Verilog/System Verilog; from Micro-architecture to Front-end Design.
Support the interface as an integratable IP for internal and external customers.
Generate collateral (Field Programmable Gate Array reference design, documentation, and training).
Work in the evolution (revolution) of the interface in subsequent product generations.
Provide architectural input in the design/integration of IP in a programmable SoC environment.
Support customers with the implementation of their logic to be tested with high-speed IOs.
Candidate must exhibit the following behavioral traits:
Critial thinking.
Effective communications skill.
Willing to work as a team and follow technical guidance.
Length of Internship: 6+ months with the possibility to extend it as per business needs
This is an entry level position, and it will be compensated accordingly.
Qualifications
You must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your schoolwork schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
The candidate must be pursuing a Master’s degree or PhD degree in Electrical Engineering, Computer Science, or related field.
6+ Months of experience in the following:
Analog and/or digital design.
Software programming Skills in Python, Verilog or C.
Preferred Qualifications
6+ Months of experience in some of the following:
MS Office Suite.
FPGAs, SERDES and networking applications.
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Other Locations
Virtual US and Canada
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Annual Salary Range for jobs which could be performed in US, Colorado:
$52,000.00-$147,000.00
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
Get email alerts for the latest"IP Subsystem FPGA Graduate Internship jobs in San jose"
