Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.

Qualifications

Master's degree in Electrical or Computer Engineering, Computer Science, or related field. 4 plus years of experience in developing testbenches using System Verilog language and UVM/OVM methodology, developing test plans, creating tests and closing functional coverage. Understanding of security principles. Experience with security test plans. Experience in programming with C/C++/Perl/Python. Experience with supporting post-silicon bring up and debug.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.

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