Required Skills: l Minimum 3 years’ experience and be a self-starter l Experience of formulating and writing System Verilog coverage statements l Good knowledge of UVM or OVM l Good knowledge of Verification Planning and Management methods l High competence with System Verilog and Verilog l Experience of creating testbenches for and testing of silicon IP l The ability to work as part of a team and under pressure is essential l Team leading experience l Fluent in English Desirable Skills: l Familiarity with SVA assertions or similar would be beneficial, though not required l Familiarity with IC design and implementation beneficial, though not required Organization: Digital Industries Company: Siemens EDA (India) Private Limited Experience Level: Experienced Professional Full / Part time: Full-time