To be eligible for participating in the C2DG contest your referral must be:

• Relevant for one of our many full-time experienced reqs (student referrals are not included)
• have experience in at least one of the technology domains according to the following profiles

Logic

4+ years of Experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. Experience with ASIC design verification, synthesis, timing/power analysis and DFT. Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.

DFT

4+ years of expertise in DFT insertion and analysis in complex designs like CPU, GPU, and complex networking chips. Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues. Experience with ASIC DFT, synthesis, simulation, and verification flow.

Verification

4+ years of experience in RTL verification. Working on verification concepts and tools: UVM, Coverage Driven verification. Good understanding and knowledge of object-oriented programming concepts: Verilog/ SystemVerilog/Specman

Formal verification: 2+ years of experience in Formal verification.

Arch

4+ years of Experience leading and managing core definition and design projects. Understanding and experience in one or more of the following areas: CPU performance, Power Management, cloud computing provisioning, migration, fault tolerance, management; thermal modeling; network-on-chip design; modeling; performance and/or Memory subsystem design.

Hardware Backend

4+ years of experience in physical design flow (“RTL to GDS”); Deep understanding in sign-off activities (timing and physical verification).

Analog Layout

4+ years of experience as an Analog/IO VLSI circuit design engineer. Knowledge in VLSI Analog and Digital circuits design, and layout. High-speed Analog IO design and PHY architectures.

Software Engineer

4+ years of experience in OOP programming in an integrated SW environment

Experience in Perl/Python, C++ and Linux OS

Relevant locations: Haifa, Petah Tikva, Beer Sheva and Jerusalem.

** Please be informed that Intel is proactively trying to find candidates for the positions and that those positions may not be available at this time.

Qualifications

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations
Israel, Jerusalem; Israel, Petah-Tikva;